(151c) Pretreatment and Copper Ion Diffusivity Optimization in High Speed Cu Pillar Electroplating for CMOS Packaging

Cu pillar used in CMOS packaging refers to a high aspect ratio column structure formed by high-speed copper electrodeposition to provide electrical connection between chips and substrates. Cu pillar not only provides electrical connection between layers but also offers structural benefits in addressing heat dissipation issues in advanced AP chips. In addition, Cu pillar replaces the present solder bump with a solid pillar structure, reducing the number of substrate layers, lowering production costs, and enabling finer chip connections. Cu pillar is mainly used to connect front RDL (Redistribution layer) and backside RDL in FOWLP (Fan-Out Wafer Level Package), and is also utilized in advanced high-density packages such as CoC (Chip on Chip) and TSV (Through Silicon Via).

In this study, we established a wafer pretreatment method prior to the Cu pillar plating process and optimized the diffusion of copper ions on the seed surface for high-speed plating without any defects. We ensured sufficient wettability of the wafer for plating solution and improved the surface condition of the wafer to increase the reliability of the Cu pillar plating process through wafer pretreatment. In addition, we quantified the diffusivity of copper ions under various process variable changes to optimize the Cu pillar plating process.