(434a) End-to-End Design and Implementation of Robust MPC on Resource-Limited Hardware Using Multi-Objective Bayesian Optimization and Deep Learning

The increasing need for optimal control of complex and safety-critical systems has been a driving force for the development of robust and stochastic model predictive control (MPC) strategies [1]–[3], which can systematically account for uncertainties within the system and its environment. Despite their development, there remains a crucial hurdle in their ultimate implementation, in particular for fast-sampling systems. Inevitably, such robust strategies add a layer of complexity to the optimal control problem, increasing the computational requirements of the controller. On the other hand, the desire to implement such controllers on embedded hardware poses a unique challenge in controller design that involves a trade-off between performance and robustness and/or physical hardware restrictions. In particular, expansion of the processing power of modern hardware relies on the use of so-called hardware accelerators (e.g., graphics processing units (GPUs), field programmable gate arrays (FPGAs), etc.), which must be programmed specifically to speed up particular portions of computational algorithms [4]. Thus, to take full advantage of the speedup offered by these hardware accelerators, the hardware-software co-design process should be simultaneously optimized with respect to performance, robustness, and hardware utilization.

In this work, we propose a framework for the automated generation of approximated robust MPCs on FPGAs for advanced control of constrained, nonlinear systems. This framework provides an automatic means to efficiently select parameters that affect the performance, robustness, and embeddability of a controller on resource-restricted hardware. Our framework includes the use of approximate controllers to replace the online evaluation of MPC [5]–[8], the use of the high-level synthesis workflow to automatically generate hardware-ready code [9], and the use of multi-objective Bayesian optimization [10], [11], which balances the trade-off between performance, robustness, and embeddability, to optimally select controller design and implementation parameters. We use deep learning to approximate a robust MPC [6], [12], which offers two key advantages: (i) an explicit approximation of the complex robust MPC structure that can be quickly evaluated and (ii) a predefined structure for which the hardware design can be tailored for easier deployment. Once an approximate controller has be generated, embedded implementation on a FPGA requires the translation of the software-based algorithm to the hardware level. Here, we rely on the high-level synthesis workflow, which is a two-step process that takes in a high level description of the controller algorithm which should be sped up and converts it to a hardware description language (HDL) [9]. Then, the HDL code can be used to program the FPGA device. As opposed to a completely software-driven approach, the inclusion of a hardware accelerator allows for the use of more complex algorithms without significant loss of computational speed. Furthermore, the combination of prescribing a computational architecture with deep neural networks (DNNs) and the hardware synthesis provides an end-to-end controller design workflow, of which allows for fully automated optimization of the implemented controller.

Finally, within this design process, we encounter many controller design parameters related to the algorithm development, including robust MPC tuning parameters, data generation for the DNN approximation, DNN structure, DNN training, and hardware-specific design parameters, including numerical representation and parallelization of computations. The choice of such parameters is not trivial since each can affect each of the competing metrics (i.e., performance, robustness, and ultimate embeddability) in differing, implicit, and non-intuitive ways. Furthermore, the entire design process (from software-based controller synthesis to hardware implementation) can take an extended period of time to complete, making the systematic selection of design parameters highly valuable. For this purpose, we use Bayesian optimization (BO) [13], which is a data-driven optimization strategy to handle black-box and expensive-to-evaluate metrics. Recently, BO has been used for a variety of tuning functions in this framework, particularly in hyperparameter selection for deep learning [14] and auto-tuning of controllers [15]. Furthermore, to highlight the trade-off between each of the controller design metrics, we use a multi-objective approach to directly compute the Pareto frontier [10]. In this manner, we find the set optimal configurations and the ultimate decision between performance, robustness, and embeddability of a particular controller can be determined based on the system requirements.