(591c) Early Experiences With the Intel Xeon Phi and MIC Architecture | AIChE

(591c) Early Experiences With the Intel Xeon Phi and MIC Architecture

Authors 

Willmore, F. T. - Presenter, National Institute of Standards and Technology



Recent advances in High Performance Computing Architecture include General Purpose Graphics Processing Units, originally co-opted from gaming, have already seen wide adoption as accelerators in computational chemistry and scientific computing. Mindful of the ever-increasing power requirements of HPC as technology pushes towards the exascale, and with the release of the ARM64 standard, curious eyes are on the confluence of companies developing ARM-based processors for battery-powered mobile devices, hoping to leverage another consumer product for scientific computing. Meanwhile, Intel has released its own accelerator solution in the form of MIC (Many Integrated Core) technology as seen in the Intel Xeon Phi product line, now deployed and available to the open science community as TACC Stampede.

As part of its mission of enabling scientific discovery through advanced computation and in addition to the deployment of world-class computing systems, the Texas Advanced Computing Center, a research unit of the University of Texas at Austin, strives to evaluate new hardware architectures for potential applications to the computational science community. Some early results on performance, scaling and discussion of competing new technologies for molecular science applications will be presented.

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