(707e) Interface Thermal Transport Measurements across Nano-Junctions

With increased miniaturization of electronic devices and consequently increased integration density, effective dissipation of heat stands out as one of the most important factors dictating performance efficiency and sustainability of the devices. Thermal management and fundamental research on thermal transport properties in low-dimensional nano-structures is thus crucial for engineering high performance devices. Moreover, nanotechnology based devices contain a large number of interfaces and junctions, and transport across the junctions plays a major role in device operation. The present paper aims at reporting proof-of-concept demonstration of measurement of interfacial thermal resistance (ITR) by an AFM based technique. Topographic imaging is used to locate the nano-structures and then electric current is passed through the circuit formed by the nano-structure patterned on a dielectric layer, two current-carrying electrodes on the substrate, a known macroscopic resistor and an external power supply. A set of two electrodes taps the voltage drop across the nano-structure on the dielectric. Due to passive heating across the nano-structure, the resistance changes resulting in a dc voltage drop across the wire from which the rise in temperature due to ITR is computed by fitting the experimental data to the theoretical model, knowing temperature coefficient of resistance. The rise in temperature across the nanowire-substrate interface, in turn, gives the ITR. Alternatively, the 3ω method has been used to monitor the temperature when an AC current replaced the DC. This work presents the technique along with the measurements of nano-interface thermal resistance of nanowire-substrate junction using the aforesaid technique.