(64e) Enhanced Performance of Pid Controller Design for Second–Order Processes with Time Delay
AIChE Annual Meeting
2007
2007 Annual Meeting
Process Development Division
Advances in Microprocessing Engineering
Monday, November 5, 2007 - 2:10pm to 2:35pm
A design method for a proportional?integral?derivative (PID) cascaded with a lead-lag compensator is proposed for enhanced disturbance rejection of the second-order stable and unstable processes with time delay. A two-degree-of-freedom control scheme is used to cope with both regulatory and servo problems. An ideal feedback controller equivalent to IMC is obtained through the IMC design principle, and is further simplified to the PID cascaded with a first-order lead-lag compensator. The simulation is conducted for a broad class of stable and unstable processes and the results are compared with those of recently published PID type controllers to illustrate the superiority of the proposed controller. For a reasonable comparison, the controllers in the simulation study are tuned to have the same degree of robustness by measuring the maximum sensitivity, . The robustness of the controller is also investigated by simultaneously inserting a perturbation uncertainty in all parameters in order to obtain the worst-case model mismatch. The proposed method illustrates greater robustness against process parameter uncertainty.
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